Flash EEPROM memory arrays have been used in personal computers as a type of long term memory. For example, a flash EEPROM memory array may be used in place of a hard disk drive as described in U.S. Pat. No. 5,822,781, entitled “Sector Based Storage Device Emulator Having Variable-Sized Sector”, issued to S. Wells on Oct. 13, 1998, and assigned to the assignee of the present invention. Such a flash memory array provides a smaller, lighter, functional equivalent of a hard disk drive and is not as sensitive to physical damage. Such a flash memory array would be especially useful in portable computers, where space and weight are important considerations. However, these flash EEPROM memory arrays may also require much higher voltages and substantially more power than that directly available from the batteries of low power portable computers.
Typically, a flash memory array is subdivided into blocks and the erase mode may erase one or more blocks of memory cells. The flash memory cell may be erased by removing excess charge from the floating gate. The conventional method of erasing all the cells in a block of flash memory requires the application of 12 volts to the source terminals of all of the memory cells in the block while the drain terminals are left floating and the gate terminals are grounded. Flash memory cells may be programmed by placing excess charge on the floating gate to increase the threshold voltage of the flash memory cell. Programming is typically achieved by applying approximately 11-12 volts to the gate, 6-7 volts to the drain, and grounding the source terminal so that electrons are placed on the floating gate by hot electron injection. Flash memory cells can be read by applying a fixed voltage to the gate of the flash memory cell in order to determine whether the flash memory cell is in an erased or a programmed state. This technique senses the drain-to-source current, Ids, for the flash memory cell. Reading a flash memory cell typically requires the application of 5 volts to the gate, 1 volt to the drain, and grounding the source terminal. Thus, typical voltages required for flash memory applications include 5 volts for the read mode and 6 and 12 volts for both the program and erase modes.
Power for the flash memory device can be provided by a Vcc line and a Vpp line. The Vcc line is the primary power source for the flash device. The supplemental voltage provided by supply line, Vpp, is typically needed only when writing or erasing the memory because of the higher voltages needed during those operations. Vcc can be approximately 5 volts. Vpp, however, might be 3.3, 5, or 12 volts.
When Vpp is large, a correspondingly large voltage stress is encountered by the field effect transistor devices that pass Vpp to the internal nodes of the Flash chip. The high voltage stresses in turn cause premature breakdown of the transistors. Accordingly, transistors capable of tolerating high voltage stresses are suitable for such applications. Field effect transistor devices with thick oxide layers are relatively tolerant to sustained voltage gradients across their gate oxide on the order of 12 volts. However, since such thick oxide devices have a low transconductance (low GM), they have to be made very large to minimize the voltage drop across them. Such transistors can occupy an undue amount of chip surface area and disadvantageously increase chip size and production cost.
Thin oxide transistor devices such as S devices and P devices occupy much less space on the chip, but generally are not capable of withstanding the voltage stress caused by direct coupling to a sustained power pad voltage. Over time, the large voltage gradient can cause the oxide layers of such S and P devices to fail. For this reason, thick oxide transistor devices have typically been used in protection circuit applications.
Like reference symbols in the various drawings indicate like elements.